1. Field of the Invention
The present invention relates to a technique for preventing cracking of a wafer in a wafer process for manufacturing semiconductor devices such as light-emitting elements and light-receiving elements.
2. Description of the Background Art
Processing of devices using InP and GaAs may cause cracking of an epitaxial wafer during the process. When a 2-inch or 3-inch wafer is processed, cracking of the wafer during the process makes it impossible to further continue the process and thus makes the wafer defective.
Although the process may be continued using a cracked wafer, transport and lithography become difficult because of the indeterminate form of pieces of the broken wafer. Therefore, it is necessary to find conditions suitable for the form and to manually process the pieces. Even when a device is manufactured on a piece of the broken wafer by various techniques in a time-consuming manner, much labor is required, thereby increasing the cost.
Herein, a light-receiving element is described. FIGS. 1A to 1F are longitudinal sectional views of one chip showing transitions in a process of manufacturing a pin-photodiode for fiber-optic communication. First, a S (sulfur)-doped InP substrate 2 having a diameter of 2 inches or 3 inches is prepared as a substrate. The sulfur-doped InP substrate 2 is an n-type.
As shown in FIG. 1A, a nondoped InP buffer layer 3 having a carrier concentration n of 1×1015 cm−3 and a thickness d of 2.0 μm, an InGaAs light absorption layer 4 having a carrier concentration n of 1×1015 cm−3 and a thickness d of 3.5 μm, and an InP window layer 5 having a carrier concentration n of 1×1015 cm−3 and a thickness d of 1.5 μm are epitaxially grown on the n-type InP substrate 2. The InGaAs light absorption layer 4 has a thickness of 3 to 4 μm so that light at 1.3 μm to 1.55 μm for fiber-optic communication can be sufficiently absorbed. In this case, d=3.5 μm. The wafer 2 serves as a substrate, and the InP buffer layer 3, the InGaAs light absorption layer 4, and the InP window layer 5 which are formed on the substrate are referred to as an “epitaxial layer 40”. Such a wafer in which the epitaxial layer 40 is formed on a mirror wafer is referred to as an “epitaxial wafer 20”.
Then, the steps of p-type dopant diffusion and electrode formation are performed. These steps are referred to as “processing steps”. The processing steps include heating, cooling, film formation, etching, transport, and polishing steps. Therefore, external force such as heat strain and physical impact is applied to the epitaxial wafer. As a result, the wafer may be broken during processing. The processing steps applied to the epitaxial wafer are described with reference to FIGS. 1B to 1F.
First, a mask is formed for forming a p-type region. A SiN film 7 (or a SiON film) is deposited on the epitaxial wafer by a CVD method. The thickness of the SiN film 7 is 100 nm to 200 nm. The wafer is strongly heated in the CVD method. Next, the SiN film 7 is partially etched in a portion corresponding to the central portion of the element unit to form a mask opening. The circumferential portion remains covered with the SiN film 7. The epitaxial wafer 20 having the mask and Zn3P2 (zinc phosphide) used as a diffusion raw material are vacuum-encapsulated in a quartz ample. The ample is placed in an electric furnace and heated at 520° C. for 30 minutes to thermally diffuse Zn from the opening.
As shown in FIG. 1B, zinc (Zn) is thermally diffused to form a p-region 6 extending from the opening (central portion of the element) to the InP window layer 5 and the InGaAs light absorption layer 4. Consequently, a p-n junction is formed in the InGaAs light absorption layer 4. The ends of the p-n junction are protected by the SiN film 7.
Next, an antireflection film 8 is formed over the entire surface of the wafer. The antireflection film 8 is, for example, a SiON film. This film is also formed in about 100 nm to 200 nm thickness by the CVD. FIG. 1C is a sectional view showing an element unit provided with the antireflection film 8. A mask and resist are applied, and the antireflection film is removed from a portion corresponding to a portion of the p-region by lithography. Then, a AuZn film is deposited, and a AuZn electrode 9 can be formed using a liftoff technique. FIG. 1D is a sectional view showing the element after the formation of the p-electrode.
The InP substrate 2 is thinned by polishing the back of the substrate 2. For example, the InP substrate having an initial thickness of 350 μm is polished to about 200 μm. Thinning of the chip facilitates a process of dividing a wafer into individual chips. In the case of a laser diode, a substrate is polished to increase heat dissipation capacity. FIG. 1E shows the InP substrate which has been thinned by polishing until the shape can be physically maintained. Further, a AuGeNi film is formed on the back of the wafer and then partially removed to form an n-electrode 10. As a result, a light-receiving element as shown in FIG. 1F can be formed. When the n- and p-electrodes are reversely biased, light is incident from above, and reach the p-n junction through the p-region 6, a photocurrent occurs.
The epitaxial wafer has a diameter of 2 inches or 3 inches. A photodiode chip has a 300 μm to 500 μm-square shape. In a photodiode for detecting signals, the diameter of a light absorption portion is about 50 μm. In a monitor photodiode for monitoring laser output, the diameter of a light absorption portion is about 200 μm.
The zinc selective diffusion, antireflection film formation, p-type electrode formation, back polishing, and n-type electrode formation shown in FIGS. 1B to IF may be referred to as a “wafer process” because they are performed directly in a wafer form. Herein, these are referred to as “processing steps”. Although the epitaxial wafer is a complete circular wafer, the wafer may be broken during the processing steps. FIG. 2 shows an example of the epitaxial wafer 20 broken during the processing steps. The linear portion on the proximal side is an orientation flat 22. In this example, there a longitudinal linear crack 23 and a transverse crack 24. The broken wafer is separated into three pieces 28, 29, and 30.
In both transport and mask alignment, the same processing steps as those for the whole wafer cannot be used for the pieces. When the processing steps are performed for each of the pieces, a manual labor is required. FIG. 3 also shows an example of a broken wafer. In this example, oblique cracks 25, 26, and 27 occur. The wafer is broken into indeterminate-form pieces 32, 33, and 34. It is difficult to perform the processing steps for such indeterminate form pieces even by a manual labor. Although, in each of the above-described examples, the wafer is broken into three pieces, the wafer may be broken into two or four pieces.
When photodiodes are manufactured using a 2-inch InP epitaxial wafer as a substrate, the processing steps cause cracking at a probability of as high as 30% or more. A 3-inch InP epitaxial wafer is broken at a probability of about 40% or more. Processing a broken wafer by a manual labor increases the cost. However, when the broken wafer is disposed of, the yield in a wafer stage is lowered, thereby increasing the cost as a whole.
Patent Document 1 U.S. Pat. No. 5,212,394
Patent Document 1 relates to a problem in which in a compound semiconductor heteroepitaxial wafer, i.e., a GaAs or InP heteroepitaxial wafer, dislocations extend from the end toward a center or cracks occur at the end. This document describes that unlike a Si wafer, a compound semiconductor wafer is not technically matured yet and thus has many problems of dislocation and breakage. In heteroepitaxial growth, there are many dislocations and other defects in a circumferential portion while no dislocation is present in a central portion. The document also describes that dislocations and defects propagate toward a central portion due to heating and impact in the wafer process, thereby degrading the quality of an epitaxial layer in the central portion.
Therefore, as shown in FIG. 5 of Patent Document 1, an annular groove 35 is provided in a circumferential portion of an epitaxially grown epitaxial wafer 20 in order to separate an epitaxial layer 37 in the circumferential portion from an epitaxial layer 36 in the central portion. Dislocations 38 present at a high density in the circumferential portion are cut off by the annular groove 35. The dislocations 38 do not enter the central portion 36. Patent Document 1 describes that the epitaxial layer in the central portion is protected during the wafer process. This means that diffusion of the high-density dislocations in the circumferential epitaxial layer into the central epitaxial layer is cut off by the annular groove. Unlike in Patent Document 1 in which a problem is to prevent propagation of dislocations, in the present invention, cracking of a wafer is considered as a more important problem. However, since the present invention is slightly similar to Patent Document 1 in that an annular groove is formed, Patent Document 1 is described herein.
When an epitaxial layer is provided on a compound semiconductor wafer such as an InP substrate or a GaAs substrate and then subjected to processing steps, the wafer is broken at a probability of as high as 30% to 40% as shown in FIG. 2 or 3. The arcuate pieces 30, 28, and 29 having a relatively regular shape can be continuously subjected to subsequent processing steps (p-n junction formation, antireflection film formation, formation of p- and n-electrodes, etc.) by a manual labor. However, the wafer to be handled is not a standard circular wafer, a manual labor is required, and efficiency is decreased to increase the required time. As a result, the workload is increased to increase the cost.
The indeterminate form pieces 32, 33, and 34 are difficult to process even by a manual labor. Consequently, the pieces 32, 33, and 34 are disposed of. Therefore, when an epitaxial wafer is broken, the efficiency of processing steps is decreased to increase the cost. In addition, the waste amount is undesirably increased.